Linux Foundation RISC-V Foundational Associate

To read any instruction set you need the machine model beneath it. You review registers, memory and the fetch-decode-execute cycle, and what makes RISC-V a load-store, reduced instruction set design.

• Registers, memory and the program counter
• The fetch, decode and execute cycle
• RISC and CISC compared
• Load-store architecture
• Byte order and alignment
• Binary, hexadecimal and two’s complement

You build A paper simulation of a small program stepping through a simple RISC-style machine.

The base ISA is small enough to learn whole. You study the integer registers and their conventional names, the instruction groups, and what changes between the 32-bit and 64-bit variants.

• The 32 integer registers and the hardwired zero register
• ABI register names: arguments, temporaries, saved, stack
• Arithmetic, logic and shift instructions
• Loads and stores
• Branches, jumps and calls
• RV32I and RV64I differences

You build A reference card for the base integer instructions, with a worked example of each group.

Every RISC-V instruction is a 32-bit pattern with a regular layout. You learn the six formats, how immediates are scattered across bits, and how to decode and encode an instruction by hand.

• The R, I, S, B, U and J formats
• Opcode, function and register fields
• How immediates are encoded
• Decoding an instruction from hexadecimal
• Encoding an instruction by hand
• The compressed instruction idea

You build A small decoder program that turns machine words into assembly text, checked against a disassembler.

RISC-V is modular: a base plus extensions you choose. You learn what the standard extensions add, how ISA names such as RV64GC are read, and how to find which extensions a processor supports.

• The modular approach to an ISA
• Multiply and divide, atomics and compressed instructions
• Single and double precision floating point
• Vector and other ratified extensions in outline
• Reading an ISA string such as RV64GC
• Detecting extensions on a real or simulated core

You build An ISA string decoder and a table showing which extension supplies each instruction in a sample program.

Assembly makes the machine visible. You learn the syntax, directives and pseudoinstructions, write loops, conditionals and functions, and see how a few instructions become a complete program.

• Assembler syntax, labels and directives
• Pseudoinstructions such as li, la, mv and call
• Conditionals and loops
• Arrays and strings in memory
• Functions, call and return
• Data sections and constants

You build A set of small assembly programs: string length, array sum and a recursive function.

Finding faults in assembly means watching registers and memory change. You run code in a simulator, step through it in a debugger, compare hand-written code with compiler output, and reason about performance.

• Running programs in QEMU or Spike
• Stepping and inspecting with GDB
• Breakpoints, watchpoints and registers
• Converting a C function to assembly by hand
• Comparing your code with compiler output
• Counting instructions to judge performance

You build A debugging session transcript that finds three planted bugs in assembly programs.

Software at different levels of trust runs in different modes. You learn machine, supervisor and user mode, read and write control and status registers, and follow how exceptions and interrupts are handled.

• Machine, supervisor and user modes
• Control and status registers
• Reading and writing CSRs from assembly
• Exceptions, interrupts and traps
• Trap vectors and saving state
• System calls with ecall

You build A trap handler that catches an illegal instruction and a system call, reporting the cause register.

Memory behaves differently on a multicore machine than on paper. You learn the RISC-V memory model, the fences that order accesses, and how page tables translate virtual addresses to physical ones.

• The RISC-V weak memory model in outline
• Fences and atomic operations
• Virtual memory and page tables
• Sv32 and Sv39 translation schemes
• Page faults and the satp register
• Physical memory protection in outline

You build A hand-built page table that maps a small region, with a walk-through of one address translation.

Most RISC-V software begins as C. You cross-compile with a toolchain, learn how the calling convention uses registers and the stack, read disassembly, and mix in inline assembly where needed.

• Cross-compilers, assemblers and linkers
• Compiling for a target ISA and ABI
• The calling convention and stack frames
• Disassembling with objdump
• Inline assembly and when to use it
• Linker scripts and memory layout

You build A C program compiled for RISC-V, with its stack frame and disassembly annotated by hand.

RISC-V runs everything from tiny controllers to servers. You compare microcontrollers and application processors, follow the boot path from firmware to an operating system, and see how a general-purpose OS runs applications.

• Microcontrollers and application processors compared
• Boot flow: ROM, firmware and bootloader
• The supervisor binary interface and OpenSBI
• A small real-time kernel versus Linux
• Running Linux and its applications on RISC-V
• Choosing a core for a product

You build A boot-flow diagram for one RISC-V board, with each stage and its privilege mode marked.

Take code from source to a running system. You write C and assembly, build with a cross toolchain, boot it in a simulator, handle a trap, and debug it, explaining each layer you touched.

• Planning a small bare-metal program
• Writing start-up code in assembly and logic in C
• Building with a linker script
• Booting and debugging in a simulator
• Handling a trap and reporting the cause
• Explaining the stack from ISA to program

You build A bare-metal program that boots in a simulator, prints output, handles a trap and ships with annotated source.